1. Field of the Invention
This invention relates to ferroelectric field effect transistors, and more particularly to ferroelectric memories utilizing such transistors and methods of fabricating such transistors and memories.
2. Statement of the Problem
It has been known since at least the 1950's that if a practical ferroelectric memory could be made, it would provide a fast, dense, non-volatile memory that could be operated at relatively low voltages. See Orlando Auciello et al., "The Physics of Ferroelectric Memories", Physics Today, July 1998, pp. 22-27. The principal type of ferroelectric memory being explored today is the non-volatile ferroelectric random access memory or NVFRAM. Ibid. A disadvantage of the NVFRAM is that, in the process of reading it, the information it holds is destroyed and, therefore, the read function must be followed by a rewrite function. Destructive reading followed by rewriting generally requires operating a memory with two transistors and two capacitors ("2T-2C"), which reduces overall circuit density and efficiency, as well as increase manufacturing costs.
It has been postulated for at least 40 years, however, that it may be possible to design a nonvolatile, nondestructive read-out ("NDRO") memory in which the memory element is a single ferroelectric field effect transistor ("FET"), thereby reducing at least some of the complexity of conventional 2T-2C operation. See Shu-Yau Wu, "A New Ferroelectric Memory Device, Metal-Ferroelectric-Semiconductor Transistor", in IEEE Transactions On Electron Devices, pp. 499-504, August 1974; S. Y. Wu, "Memory Retention and Switching Behavior Of Metal-Ferroelectric-Semiconductor Transistors", in Ferroelectrics, Vol. 11, pp. 379-383, 1976; and J. R. Scott, C. A. Paz De Araujo, and L. D. McMillan, "Integrated Ferroelectrics", in Condensed Matter News, Vol. 1, No. 3, pp. 15-20, 1992. Because the ferroelectric memory effect measured in the early devices of Wu was only a temporary, single state effect rather than a long-lived, two state effect, it is now believed that this effect was charge injection effect rather than an effect due to terroelectric switching.
A structure well-known in the art is the so-called metal-ferroelectric-semiconductor FET ("MFS-FET"), in which a ferroelectric layer is formed on the semiconductor substrate, and the metal gate electrode is located on the ferroelectric layer. Typically, the ferroelectric layer comprises a ferroelectric metal oxide. When a ferroelectric metal oxide, such as PZT, is formed directly on a semiconductor substrate, such as silicon, high leakage current, low retention times and fatigue are common problems. It is commonly believed in the art that some of this is a result of a poor interface between ferroelectric oxides and silicon. The poor interface may be a result of incompatibility of crystalline ferroelectric oxides with the crystal lattices and thermal coefficients of silicon.
Also, when a thin film of ferroelectric oxide is in direct electrical connection with the gate oxide layer of the transistor gate, it is difficult to apply sufficient voltage to the ferroelectric thin film to switch its polarization. A ferroelectric thin film and a gate oxide may be viewed as two capacitors in series. The dielectric constant of the ferroelectric thin film (usually 100-1000) is much higher than the dielectric constant of typical gate oxides (usually about 3-5). As a result, most of the voltage drop occurs across the low dielectric constant material, and an extra high operational voltage is required to switch the polarization of the ferroelectric thin film. This can lead to electrical breakdown of the gate oxide and other materials in the circuit. Further, a high operational voltage in excess of 3-5 volts would render the device incompatible with conventional integrated circuit art.
To reduce interface problems, structures have been designed in which an insulating oxide layer, such as CeO.sub.2 or Y.sub.2 O.sub.3, is sputter-deposited on the semiconductor substrate and the gate oxide before depositing the ferroelectric layer and gate. Such an integrated structure is referred to in the art as a metal-ferroelectric-insulator-semiconductor FET ("MFIS-FET"). Recently, a metal-ferroelectric-insulator-semiconductor FET device ("MFIS-FET") has been reported that appears to show true ferroelectric memory behavior. See Tadahiko Hirai et al., "Formation of Metal/Ferroelectric/Insulator/Semiconductor Structure With A CeO.sub.2 Buffer Layer", in Japanese Journal of Applied Physics, Vol. 33, Part I, No. 9B, pp. 5219-5222, September 1994; Tadahiko Hirai et al., "Characterization of Metal/Ferroelectric/Insulator/Semiconductor Structure With A CeO.sub.2 Buffer Layer", in Japanese Journal of Applied Physics, Vol. 34, Part I, No. 8A, pp. 4163-4166, August 1995; Tadahiko Hirai et al., "Crystal and Electrical Characterizations of Epitaxial Ce.sub.x Zr.sub.1-x O.sub.2 Buffer Layer for the Metal/Ferroelectric/Insulator/Semiconductor Field Effect Transistor", in Japanese Journal of Applied Physics, Vol.35, Part I, No. 9A, pp.5150-5153, September 1996; Yong Tae Kim et al., "Memory Window of Pt/SrBi.sub.2 Ta.sub.2 O.sub.9 /CeO.sub.2 /SiO.sub.2 /Si Structure For Metal Ferroelectric Insulator Semiconductor Field Effect Transistor", Applied Physics Letters, Vol. 71 No. 24, Dec. 15, 1997, pp. 3507-3509; and U.S. Pat. No. 5,744,374 issued Apr. 28, 1998 to Jong Moon. It is believed that an insulator layer located on the silicon substrate between the substrate and the ferroelectric thin film avoids the problems caused by a ferroelectric-semiconductor interface. Related integrated structures, in which the ferroelectric is structurally integrated with the transistor element, contain the equivalent of a floating gate electrode located between the semiconductor and the ferroelectric, and are sometimes referred to as a metal-ferroelectric-metal-insulator-semiconductor ("MFMIS-FET") or a metal-ferroelectric-metal-semiconductor ("MFMS-FET"), depending on the presence of an insulating layer.
The MFS-, MFIS-, MFMS- and MFMIS-FET and other related structurally integrated memories also share the problem of being structures that are fundamentally different from the structures of commercially fabricated ferroelectric random access memory ("FeRAM") and dynamic random access memory ("DRAM") cells, of which the fabrication processes have been proven and perfected. Therefore, expensive and time-consuming development of commercially effective fabrication processes and corresponding investment in new manufacturing facilities will be necessary before MFIS-FETs and related integrated structures can be commercially available.